The increasing integration density and also the progressive complexity of electronic circuit units (electronic chips) result in increased requirements when testing these circuit units. At present, up to 256 electronic chips are simultaneously introduced into a test device (tester) and tested by machine. In this case, there are typically 66 connection pins (pins) per electronic chip.
Test signals or test sequences are applied to specific pins and an output signal (actual signal) which is reproduced by the electronic chip can then be compared with a predetermined test sequence (desired signal) in the tester. The functionality of the chip is determined in this manner. When faults occur in electronic chips, the possibility of providing an automatic repair mechanism is increasingly being provided in mechanical testers. Said automatic repair mechanism comprises, for example, electronic fuses (“e-fuse self-repair”) such that defective memory cells, for example, are switched off and/or bridged.
Such complicated elimination of individual faults is accompanied by individual addressing of individual electronic chips. Individual addressing of individual electronic chips disadvantageously conflicts with increasing the parallelism of testing and thus shortening the test duration.
Shortening the test duration is directly accompanied by economic aspects since different test runs—for example at different temperatures—have to be provided for the chips to be tested. Different currents and internal voltages furthermore have to be individually detected in a test flow.
The requisite separate selection of electronic chips is conventionally provided, for example, by switching the supply voltage source for the corresponding chip. This is effected in such a manner that, from a group of electronic chips which are to be tested in parallel (circuit units to be tested) and are thus completely or partially connected to the same tester channels, an electronic chip is selected by switching off the supply voltage of all other electronic chips in said group.
Disadvantageously, this concept is not suitable for future test setups since parallelism of the voltage supply must also be provided, that is to say future test setups will provide supply voltage sources for a plurality of electronic chips, with the result that this type of selective addressing will not be able to be carried out. Economically, it is problematical that the test costs are taking up an ever increasing portion of the production costs. It is therefore necessary to drastically increase the number of electronic chips (electronic modules) which can be simultaneously tested on a test system in such a manner that the parallelism of testing increases. In accordance with the prior art, a signal generated by the tester or the test system is applied to a plurality of different electronic chips to be tested. However, the conventional methods disadvantageously no longer allow the individual electronic chip to be tested to be individually addressed. This fact prevents future requirements from being met in the case of e-fuse self-repair of memory modules or in the case of individual driver calibration (OCD) of DDR (Double Data Rate) II technology, in which individual addressing of electronic chips—together with highly parallel measurement at the same time—is absolutely necessary.